Field Effect Transistor with Tunable Gate Bias

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Intellectual Property

ID:		UML 05-04
IP Type:		Licensable Technology
Title:		Field Effect Transistor with Tunable Gate Bias
Inventor:		Samson Mil'shtein
Summary:		The inventors have conceived of a field effect transistor with a tune-able gate bias. The transistor comprises two gates stacked on top off each other, and separated by a Silicon-Nitrogen insulator. The top gate is longer than the bottom gate and extends closer to the drain than the bottom gate. The biases of the gates are independent of each other and tuned to produce a more uniform electrical field along the channel. The design of transistors is flexible in that the vertical distance between the tail of the top gate and the channel, as well as the horizontal distance between the end of the top gate and the drain can be varied, which allows for minimization of the total gate capacitance.
Tech Type:		Semiconductor
URL:		http://www.uml.edu/cvip
Contact:		Susu Wong, 978 934 4722, susu_wong@uml.edu
Organization:		University of Massachusetts Lowell

Display all intellectual properties for Samson Mil'shtein
Display all intellectual properties for University of Massachusetts Lowell